Break-even utilization rate measures the level at which a foundry's revenue exactly covers its costs. Below that level the business loses money, above it every additional wafer adds profit. TSMC, the world's largest foundry, can now run profitably at the operating income level at just 25% utilization (1Q26). The company could lose 75% of its current wafer demand and still cover depreciation, R&D, and SG&A. This number sat above 40% through the 2008 to 2018 FinFET decade

Today it sits at 25%, even with advanced nodes (7nm and below) climbing to 75% of wafer revenue in 2025, the most depreciation-heavy mix in TSMC's history. Pricing power, manufacturing yield, and disciplined capacity build-out drove a 2.5x increase in blended ASP between 2018 and 1Q26, overpowering the depreciation drag from 5nm, 3nm, and now 2nm ramps.

No rival comes close. UMC operates at a 48% OPM break-even and SMIC sits at 63%, both 23 to 38 percentage points worse than TSMC. SMIC runs its fabs at 96% utilization and still produces only single-digit operating margins, so it carries no cushion. Intel Foundry and Samsung Foundry remain in operating loss territory on standalone reporting.

TSMC's advantage compounds because it charges ASPs no rival can match, its depreciation intensity falls as revenue outpaces capex, and its OpEx grows with revenue instead of ahead of it. Every other foundry runs in the red at utilization levels where TSMC still earns operating income. With $56B of capex committed for 2026 and Arizona, JASM, and Dresden absorbing fresh depreciation, TSMC's break-even utilization may rise to 30 to 35% in 2027 and 2028, but that level will still sit below where its closest rivals operate today.

Our Foundry Model tracks utilization rates, process node mix, and wafer demand dynamics across every major foundry quarter by quarter. Reach out to sales@semianalysis.com if you want to explore.

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